A lower-level unfolded and higher-level folded multi-level discrete wavelet transform architecture in single-clock domain is proposed. A three-input line-based scanning method is adopted. The first-level discrete wavelet transform is designed based on the 9/7 discrete wavelet transform lifting scheme. The partially folded second-level discrete wavelet transform is constructed according to the ratio of clock cycles to valid input data. The third-level and higher-level discrete wavelet transform architectures are folded into the second-level discrete wavelet transform architecture to reduce the consumption of hardware resources. The results show that for the input image with size of 512 pixel×512 pixel processed by the three-level discrete wavelet transform, the hardware efficiency of the proposed architecture increases over 57.1% compared with the existing architectures.