In conventional SAR ADC, most time of every conversion cycle is used for quantization, and only a little time is left for sampling, thus high driving capability buffer and low Ron sampling switch are indispensable. Otherwise, serious nonlinearity will generate. The proposed time-interleaved sampling architecture could extend the sampling time of SAR ADC to equal to quantization time without reducing the quantization time and conversion rate, thus greatly reducing the power consumption of ADC driver. This paper designed and implemented a 40 Msps 10 bit asynchronous SAR ADC based on Fujitsu 55 nm CMOS technology. The measurement results show the ENOB of the converter is 97 bit.