(a) Basic working principles of CSC

Work from Ref. [9] used a 4-nm process and high-density on-chip MIM capacitors to implement the CSC as integrated voltage regulator (IVR), for multi-core graphics processing unit (CPU) applications. It also investigated ganging multiple IVR cores to the same load domain. The extremely high maximum current density is 26 A/mm².

Work from Ref. [8] addressed this by idling certain C_Fs when supplying the lower output. Then, it incorporated the RCSC scheme to further minimize the ∆V_CFs within a wide VCR range. Fig. 2(c) shows the calculated P_CS (represented by Σ(V_CF)²) normalized to that of the direct channel switching. As seen, the C_F idling + RCSC achieves the lowest P_CS within a wide range.

(d) High power density and efficiency

As shown in Fig. 2(c), it is desirable to achieve SIDO and DISO CSC in energy harvesting systems. Work from Ref. [8] proposed a time-multiplexing control (TMC), instead of the ordered-power distributive control (OPDC), to "decouple" the input and output power.

Switched-capacitor (SC) DC−DC converter^[1] is an important alternative to inductive DC−DC converter, in terms of removing the bulky power inductor. Hence, it is widely used in low-profile, low-power applications, such as the internet of things (IoT) sensor nodes and energy harvesting^[2]. Meanwhile, considering that capacitor has a much higher energy density than inductor, high-power applications, such as fast charging, also favors the SC, using off-chip flying capacitors (C_Fs). However, conventional SC converters only feature good efficiency at fixed nominal voltage conversion ratios (VCRs). Once the VCR deviates from the nominal values, the efficiency drops proportionally^[3]. This makes the SC has "discontinuous" VCRs, which is not acceptable in high-efficiency, wide-VCR-range systems.

Furthermore, the capacitors can give a much larger instantaneous charging current than inductors can do. Consequently, the CSC converter has the potential to fulfill a fast transient response.

To address this issue, work from Ref. [4] proposed a continuously scalable conversion-ratio SC (CSC) DC−DC converter, achieving a decent efficiency over a wide VCR range. Works from Refs. [5, 6] used the CSC for maximum power point tracking (MPPT) in energy harvesting systems. In recent years, a few CSC works have emerged for extending high-efficiency VCR range^[7], single-input dual-output (SIDO) or dual-input single-output (DISO) features^[8], and higher efficiency, higher power density^{[9, 10]}. In this letter, we review these recent advancements in the CSC converter, and share several of our observations and concerns.

Work from Ref. [7] addresses this issue by using reconfigurable-V_CF CSC (RCSC). It adapted the value of M and N to the VCR, with the same design complexity (the same M + N value), as shown in Fig. 2(b). This should further extend the high-efficiency VCR range of CSC. With an overall 19.8-nF C_Fs, it achieves a maximum 39.7-mW output power.

(e) Future CSC research hot spots

The CSC’s P_CS is determined by the V_CF step size (∆V_CF), i.e. ∆V_T for the step size of the top plate and ∆V_B for that of the bottom plate. Increasing the number of the CSC phases (number of C_Fs and switches) reduces the step sizes and thus results in higher efficiency. Unfortunately, this greatly complicates the design, such as 64 C_Fs and 36 × 64 switches in Ref. [4]. Hence, under a given design complexity constraint and predefined numbers of V_T and V_B steps (M and N, respectively), the VCR with ∆V_T = ∆V_B should have the optimum efficiency. Nevertheless, if the VCR deviates from this value, such as in the example shown in Fig. 2(b), the very small ∆V_B contributes little to further P_CS reduction, while the large ∆V_T significantly increases P_CS.

The CSC converter should be able to replace the inductive converter in many applications. However, although without using a bulky inductor, the CSC greatly increases the design complexity, and thus is unfriendly to the layout/PCB design. Implementing so many off-chip C_Fs is almost impossible. This may be the reason why most works from academia focused on low-power applications. A few works from industry, with high-density on-chip capacitors, achieved high power level. Yet, such capacitors are unavailable in most fabrication processes. Therefore, reducing the complexity of CSC is essential.

Figs. 1(a) and 1(b) show the operation of the charging and discharging phases of the 2 : 1 SC converter. Following Ref. [1], we use ideal voltage sources as input voltage V_IN and output voltage V_OUT in the analysis. The DC value of the C_F is V_IN/2 when the output voltage V_OUT = V_IN/2. Fig. 1(c) shows the conceptual V_CF waveform, and the C_F charge sharing loss (P_CS) is small due to the negligible V_CF ripple. However, when we use the 2 : 1 SC converter for a V_OUT = V_IN/3 operation, the P_CS becomes significant, since the V_CF swings from V_IN/3 and 2V_IN/3. This makes the conventional SC looks "discontinuous".

(c) CSC SIDO/DISO

To extend the VCR range with high efficiency, reducing the rising and falling slopes of the V_CF is desirable, as shown in Fig. 1(d). It can be achieved by splitting the large V_CF swing into K equal steps, and the resultant P_CS should be reduced by K times^[11]. Based on this idea, work from Ref. [4] made use of multi-phase SC operation (using multiple C_Fs), generating internal voltage rails for V_CF splitting. As shown in Fig. 2(a), taking the step-down conversion as an example, each C_F connects either its top plate or bottom plate to a DC voltage (V_IN, V_OUT, or V_SS), and the other plate to different internal rails.

Ref. [9] proposed a phase-merging-turbo (PMT) technique to reduce the resistances, as shown in Fig. 2(d). It merged a certain number of internal rails, parallelizing the resistances, and hence improving the heavy-load efficiency. However, the reduced number of internal rails jeopardizes the light-load efficiency.

As shown in Fig. 2(d), with the loading circuits occupying a large silicon area, it is straightforward to overhang the C_Fs (consuming top metals) above the loading circuits for a maximum C_F value (and thus power density). Yet, this inevitably results in long overhang power delivering networks (PDNs), and hence large parasitic resistances and degraded efficiency.

Work from Ref. [10] investigated the CSC IVR in the scenario of higher V_INs for a reduced input current and possibly better system efficiency. It used a 2 : 1 conventional SC to half the input voltage of the CSC, and cascaded another 2 : 1 conventional SC for the targeted low output voltage. This somewhat resembles the design philosophy of recent hybrid DC−DC converters^[12−16], where the SC is used to reduce the voltage stress of the switches, and lower the swing of the inductor switching node. After that, outphasing is used between the SC and CSC stages, fulfilling multiple V_CF steps with a reduced number of C_Fs.

(b) Extending high-efficiency VCR range

Another issue of SIDO/DISO CSC is the large P_CS during the channel switching. Take nine-C_F SIDO CSC as an example. Fig. 2(c) shows the transient waveforms of the C_Fs, where the V_CF,n should have 2 × T_CLK delay from V_CF,n−1, where T_CLK is the clock period. During switching channel from V_BAT to V_OUT (from t₁ to t₂), it is possible to manipulate the phase of some V_CFs for small ∆V_CFs, but there still exists some large ∆V_CFs, such as V_CF9. This degrades the efficiency, meanwhile, the instantaneous large charge-sharing current may damage the switches.