When analyzing the influence of proportional gain coefficient of the loop filter in the clock recovery algorithm on system bit error rate, we find that the bit error rate of the signal first decreases and then increases with the increase in proportional gain coefficient, and the optimal proportional gain coefficient varies with received power. In response to this problem, we propose a full-digital clock recovery algorithm having a full real-time dynamic proportional gain coefficient based on Gardner algorithm to deal with power jitter channels and improve the sensitivity of the algorithm. The algorithm is then verified by online experiments in a 2.5 GBaud coherent communication system built upon the Altera Stratix-V 5SGXMA7K2F40C3 FPGA platform and quadrature phase-shift keying modulation. With the forward error correction threshold of 2×10 ^-4 in KP4 as upper limit, the dynamic parameter algorithm can reduce the minimum received power for the system to reach this threshold from -47 dBm of the fixed parameter algorithm to -49.5 dBm when the power jitter frequency is low. When the frequency is high, the lowest power and frequency of the jitter that the fixed parameter algorithm can withstand are -46.5 dBm and 100 Hz respectively, whereas those of the dynamic parameter algorithm are -50 dBm and 1 kHz respectively.