Semiconductor Optoelectronics, Volume. 42, Issue 1, 52(2021)
Performance Optimization of Long Linear Array CMOS Image Sensor
A kind of long linear array CMOS image sensor based on the capacitors trans-impedance amplifier (CTIA) is designed. A single-ended four transistors cascade operational amplifier is employed for eliminating the power dissipation and area. In order to promote the signal readout ratio, a minimized PMOS source follower without body effect is designed. The effect of the parasitic capacitance of the output bus is reduced. On the layout, the top metal is used to reduce parasitic resistance and capacitance. The signal readout ratio and the linearity range are raised. The image sensor chip with the pixel array of 5×1030 and the pixel size of 20μm×20μm is fabricated with 0.35μm standard CMOS process. Test results show that the image sensor works well when the integration time is 1ms and the readout ratio is 4MHz. The linearity can reach up to 98% and the linearity of dynamic range is 76dB.
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XU Xing, CHEN Yongping, CHEN Shijun, YUAN Honghui, WANG Xin. Performance Optimization of Long Linear Array CMOS Image Sensor[J]. Semiconductor Optoelectronics, 2021, 42(1): 52
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Received: Nov. 17, 2020
Accepted: --
Published Online: Mar. 18, 2021
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