Optics and Precision Engineering, Volume. 28, Issue 5, 1212(2020)

FPGA-based hardware acceleration for CNNs developed using high-Level synthesis

WEI Chu-liang1,*... CHEN Ru-lin1, GAO Qian2,3, and SUN Zheng-long23 |Show fewer author(s)
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  • 1[in Chinese]
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  • 3[in Chinese]
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    To accelerate the forward-propagation process of deep-learning networks, a field-programmable gate array (FPGA) hardware-acceleration system for AlexNet was developed using Vivado High-Level Synthesis (HLS), which can greatly reduce the FPGA development cost. Using Vivado HLS, developers can design hardware architectures on an FPGA platform using C/C++ code instead of a hardware-description language. We implemented AlexNet on an FPGA platform using the HLS tool, and then used the PIPELINE and ARRAY_PARTITION directives to optimize the proposed system. An evaluation of the proposed system shows that its performance is three times better than a traditional computing-platform graphics processing unit (GPU). In the future, owing to the high-level encapsulation, the developed system can be easily transformed into other convolutional neural networks for practical operation, which shows its great portability and practical application value.

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    WEI Chu-liang, CHEN Ru-lin, GAO Qian, SUN Zheng-long. FPGA-based hardware acceleration for CNNs developed using high-Level synthesis[J]. Optics and Precision Engineering, 2020, 28(5): 1212

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    Paper Information

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    Received: Dec. 10, 2019

    Accepted: --

    Published Online: Nov. 6, 2020

    The Author Email: Chu-liang WEI (clwei@stu.edu.cn)

    DOI:10.3788/ope.20202805.1212

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