In order to make the computing system with low power consumption and fault-tolerant ability, a fault-tolerant universal shift register was designed using reversible logic. A new reversible fault-tolerant gate named Parity preserving D flip- flop gate (PP- DFG) was proposed. Some circuits such as register and multiplexer were designed using PP- DFG and existing gates. Based on the above modules, the fault-tolerant reversible universal shift register was built. It was modeled in Verilog hardware description language for verification. Simulation results indicate that its logic structure is correct. Compared with the existing ones in terms of quantum cost, delay and garbage outputs, the proposed circuit not only supports fault-tolerant but also has 16%～48% performance improvement. This circuit can be used as an important storage element applied in future low-power computing system.