Results and Discussions The simulation results show that when the code length is 2×10⁵ bit, the reconciliation speed after optimization is 2.17 times that before optimization. The reconciliation speed using parallel acceleration in OpenCL/FPGA heterogeneous platform is more than 4 times that in the single CPU platform (Fig. 4). As the code rate increases, the signal noise ratio (SNR) asymptotic threshold RSN increases and the reconciliation speed decreases (Fig. 4). This is because the number of rows of the check matrix declines after the code rate increases, namely that the number of check nodes reduces, and a higher SNR is required to complete the decoding. The same reason leads to more iterations required for higher code rates, longer average reconciliation time, and lower reconciliation speed. The increase in reconciliation speed only makes sense if it ensures that the security key can be obtained. When the code rate is 0.1-0.4, the reconciliation efficiency β is higher than 95% and the security key can be obtained (Fig. 5). The multi-dimensional reconciliation algorithm requires high precision for floating-point numbers, and FPGA uses a variety of approximations in its implementation, which reducing the complexity of the implementation at the expense of computational accuracy. This leads to a higher SNR asymptotic threshold and lower reconciliation efficiency with the heterogeneous scheme. After optimizing the algorithm, the reconciliation speed of the FPGA-accelerated device already exceeds that of the GPU-accelerated device (Fig. 6). This is because loop optimization and memory optimization can significantly improve FPGA decoding performance.

Quantum key distribution (QKD) is the earliest practical technology in the field of quantum communication, which has absolute security in theory. There are two kinds of QKD systems according to their source encoding dimensions: continuous-variable QKD (CV-QKD) and discrete-variable QKD (DV-QKD). Compared with DV-QKD, CV-QKD systems have such advantages: 1) modulation and decoding of CVs do not require special devices and can be implemented effectively by standard telecommunication networks; 2) the detection efficiency of homodyne or heterodyne detector used by CV-QKD is higher than that of the single-photon detector used by DV-QKD at room temperatures. Shannon's theorem suggests that the longer code length suffices for a more stable performance. Therefore, the CV-QKD system generally adopts great code length, and the number of optical pulses involved in data reconciliation reaches 10⁵. However, such a long block length brings about a much high calculated quantity. This inevitably results in a low speed of data reconciliation, which restricts the throughput and the key rates of the CV-QKD system. Given this, the paper adopts hardware devices to accelerate the decoding process. Open computing language (OpenCL) can process data at high speed by means of parallel computation. FPGA is highly parallel and can achieve high performance with ultra-low power consumption. Therefore, the combination of OpenCL and FPGA for accelerated computing becomes a good solution.

To tackle the problem of low computing speed of data reconciliation in the current continuous variable quantum key distribution system, this paper proposes an eight-dimensional data reconciliation algorithm by adopting a high-performance FPGA board as the acceleration device on the OpenCL heterogeneous computing framework. According to the characteristics of FPGA, the algorithm is optimized as follows. 1) The expression of for loops is optimized so that the OpenCL compiler can better understand the intention of the designer to generate a more effective FPGA hardware structure. 2) Memory optimization: according to the characteristics of the belief propagation algorithm for low-density parity-check code (LDPC) decoding, a dumbbell-type core architecture and information transmission mode within and between cores is designed. 3) Aggregated access data read pattern is applied to reduce the number of parallel work items. The program written in OpenCL after the above optimization has also achieved good performance. Then, simulations are performed with the optimized algorithm on a CPU/FPGA heterogeneous platform. The results are compared with the experimental results of the CPU platform.

To address the problem of slow computing speed of data reconciliation in CV-QKD systems, heterogeneous computing is adopted to accelerate decoding. The reconciliation system takes LDPC codes close to the Shannon limit as the error correction codes and the eight-dimensional data reconciliation algorithm as the reconciliation scheme. A CPU/FPGA heterogeneous platform is built with the OpenCL framework. After a series of optimizations of the OpenCL code based on the characteristics of the FPGA, the reconciliation speed is increased by 116.72% to 97.59 kbit/s. The loop optimization provides the largest improvement of up to 56%, while the dumbbell-type core architecture can also improve performance by nearly 42% by reducing access memory consumption. Simulations are performed at different code rates on CPU and FPGA heterogeneous platforms separately. The results show that the reconciliation speed using the parallel acceleration of heterogeneous platforms is more than 4 times that of single CPU platforms. The reconciliation speed of CPU/FPGA heterogeneous platforms has exceeded that of CPU/GPU heterogeneous platforms while ensuring that a security key can be obtained.