A PGA circuit on digital double sampling ADC of CMOS image sensor is proposed. The offset voltage introduced by mis-matching of amplifier and capacitance of PGA is collected by increasing the offset sampling capacitance CC. The relative double sampling and amplification is performed in the reset sampling and PGA amplification stage, the digital double sampling ADC will quantify the two-stage storage voltage and make the difference in the digital domain, so the fixed mode noise introduced by the circuit of PGA is eliminated. Simulations were performed on 0.18μm special process of CMOS image sensor. The results show that, the output offset voltage of PGA can be reduced to less than 1mV in the range of input offset voltage of -30~30mV, which greatly reduces the column FPN compared with traditional PGA with single linear relationship between output offset voltage and input offset voltage.