A low noise and low power phase locked loop (PLL) chip for the electronic readout system of high energy physics experiments was designed and tested based on the TSMC process of 180nm. The chip was mainly composed of frequency and phase discriminator, charge pump, loop filter, voltage controlled oscillator, frequency divider and other sub-modules. In the phase-locked loop charge pump module, the cascade current mirror was used to accurately mirror the current to reduce the electrical loss and the operation amplifier clamp voltage was used to further reduce the phase noise. The test results show that the PLL chip can stably output 200MHz differential clock signal under the condition of 1.8V power supply voltage and 50MHz reference clock input. The RMS clock jitter is 2.26ps (0.45mUI), and the phase noise is -105.83dBc/Hz at the frequency offset of 1MHz. The measured power consumption of the overall chip is 23.4mW and the core power consumption of the PLL is 2.02mW.