A detailed design progress of an asynchronous two-stage pipelined SAR-ADC was introduced. In order to achieve a flexible clocking scheme, a self-synchronization loop based on an edge detector was utilized to generate an internal clock with variable phase and frequency. A tunable delay element enables to allocate the available time for the sub-ADCs and the gain-stage to reduce the static power consumption of the ADC. A 3-stage capacitive charge pump works as the gain-stage to alleviate the design difficulty and further reduce the power consumption. Finally, a 14 bit asynchronous ADC was designed and simulated in 018-μm CMOS process. Post-layout circuit simulations show that the ADC achieves a SNDR of 835 dB while consuming 239 μW with a sampling rate of 10 kS/s. The corresponding FoMs is 1767 dB.