The existing polar code soft-output decoders suffer from high resource consumption and low resource efficiency of the hardware implementation. In this paper, a Fast-RCSC decoding algorithm and its decoder hardware architecture were designed. The Fast-RCSC algorithm performed complete calculations on internal special nodes, reducing the decoding cycle while maintaining high decoding performance. Based on the similarity between different special node formulas, the resource consumption of special node modules was reduced by reusing calculation results of the introduced special node modules and reusing time-division multiplexing scheme of calculation modules. The storage resource consumption was reduced by sharing storage units and merging data with bit width lower than the limit. The synthesis results in CSMC 180 nm process show that the designed decoder has an area size of 2.92 mm2 and a resource efficiency of 245.2 Mbps/mm2 when the code length is 1 024 bits, which demonstrates different degrees of improvement compared to existing polar code soft-output decoders.