In order to match the link working mode in practical application, based on the in-depth understanding of JESD204B protocol theory, a general transmission layer circuit is designed, and the three-level mapping structure is used to realize the framing and deframing functions of the transmission layer at the sender and receiver. This paper establishes Verilog compilation simulator (VCS) verification platform for function verification. The simulation show that the circuit can complete the conversion between sampling data and frame format data according to the set link working mode, and realize the framing and deframing functions, and based on the comprehensive evaluation of 65 nm standard process library, the maximum frequency of single channel clock of the circuit is 1.25 GHz, which can reach the maximum transmission speed supported by the protocol of 12.5 Gb/s.