Scanning type infrared sensors have always been used in long-range imaging systems such as remote sensing systems, surveillance systems, satellite imaging systems, and so on^[1-4]. In these imaging systems, the infrared detector is arrayed as one or more rows, the full image is taken depending on the scanning nature of the carrier itself, such as the satellite. For the long-range application, the image quality is always affected due to the relatively lower SNR^[5-9]. TDI technique has been proposed and adopted to alleviate this problem^[10-11]. The principle of the TDI technique is straightforward: the object is scanned by several rows of detectors in a time-delayed manner, then the signals produced by pixel stages, which are corresponding to the same specific image point, are added and averaged in the TDI stage. With the add operation, the output signal is increased with the factor of n (n is the number of scanning detectors), while the uncorrelated noise is increased with the square root of the n. Therefore, the SNR is also improved with the square root of the n. The TDI algorithm is often implemented in the analog domain or digital domain. In this design, the analog TDI is chosen for its simplified realization.

To improve the resolution of the imaging system, the infrared detector chosen for the design is arrayed as shown in Fig.1. The odd and even columns are separated and placed in two different rows, enabling the horizontal overlap between the consecutive pixels. The pixel pitch between odd and even columns is designed as width as 20 μm. Two extra rows of detectors are added vertically with a 40 μm pitch. The detector is scanned with a step of 20 μm along the scanning direction. With this configuration, a scanning type infrared detector with 1024 pixels is realized with the feasibility of implementing 3× TDI.

The detector is bonded to a readout circuit (ROIC) with an indium bump. The ROIC consists of an array of capacitor trans-impedance amplifier (CTIA) circuits located under each detector pixel, column paralleled TDI stages, switch matrix to multiplex the TDI outputs, and output buffer stage to drive the large capacitive load.

The CTIA architecture is chosen as the pixel circuit to convert the photocurrent into voltage for its superior linearity and detector bias stability compared to its competitor. The detailed circuit diagram is shown in Fig.2, which is comprised of one core operational transconductance amplifier (OTA), CMOS switches, and variable integration capacitor. The offset of OTA is the main source of fixed pattern noise (FPN) in the infrared image, therefore the offset cancellation technique is introduced in the design. The CTIA operates in two phases: the reset phase and the integration phase. INT and INT_N are two control clocks with opposite phases. In the reset phase, INT_N is high, the switches S1 and S2 are closed, S3 is opened. The CTIA is configured as a unity gain buffer, the integration capacitor is reset and served to store the offset of OTA. Assuming limited voltage gain as A_v, the output voltage of CTIA is reset to

$ {V_{\rm out}} = \frac{{{A_{\rm v}}({V_{\rm REF}} - {V_{\rm os}})}}{{1 + {A_{\rm v}}}} $ (1)

Therefore, the charge stored on the left side of the capacitor can be expressed as:

$ {{{Q}}_{\rm reset}} = C({V_{\rm out}} - {V_{\rm REF}}) = - C\frac{{{V_{\rm REF}} + {A_{\rm v}}{V_{\rm os}}}}{{1 + {A_{\rm v}}}} $ (2)

When switching to the integration phase, the INT turns high, the switches S1 and S2 are opened, S3 is closed. The capacitor is connected in the feedback path between the negative input terminal and output. Neglecting the effect of charge injection and clock feedthrough, the initial output voltage of CTIA right after the switching activity can be derived from the following equation base on the charge conservation for the left plate of the integration capacitor. The formula of the charge stored and the output voltage is given by Eqs.(3) and (4).

$ {{{Q}}_{\rm reset}} = C\left({V_{\rm REF}} + \dfrac{{{V_{\rm out}}}}{{ - {A_{\rm v}}}} - {V_{\rm os}} - {V_{\rm out}}\right) $ (3)

$ {V_{\rm out}} = \dfrac{{(2 + {A_{\rm v}}){A_{\rm v}}}}{{{{(1 + {A_{\rm v}})}^2}}}{V_{\rm REF}} - \dfrac{{{A_{\rm v}}}}{{{{(1 + {A_{\rm v}})}^2}}}{V_{\rm os}} $ (4)

It is convenient to get the conclusion that the offset-induced error would be greatly reduced as long as the voltage gain is large, eliminating the offset-induced FPN that would be happened in the conventional CTIA circuit.

The detector bias is held constant due to the virtual short characteristic of the feedback, facilitating the linear response of the detector. When the photocurrent produced by the detector flows through the capacitor within the integration timing window, the output voltage of CTIA will change linearly from the initial value derived in the previous equation.

For the limited pixel area as small as 40 μm×40 μm, the OTA is designed as a differential amplifier with only 5 transistors. To accommodate the large dynamic range with photocurrent, a variable integration capacitor ranging from 5 fF to 130 fF is designed. The simulated result in Fig.3 shows less than 0.3% nonlinearity, demonstrating the advantage of the chosen CTIA circuit.

The designed TDI schematic is shown in Fig.4, where the Vi<1>-Vi<3> is the output from the previous CTIA pixel stage. As is described in the previous section, because the detector is scanned with the step of the half-pitch, the image captured by the first detector will be captured after two steps by the second detector, and four steps by the third detector. For this purpose, 5/3 capacitors are needed to sample/store the pixel output originating from the first/second detector respectively.

The TDI circuit is also operated in two phases: sampling phase and charge transferring phase. In the sampling phase, three sampling switches are closed and all the other switches are opened, the output voltages from the CTIA pixel circuits are sampled into the storage capacitors connecting to the closed sampling switches. In the transferring switches, three specific transferring switches are closed and all the other switches are opened, the charges stored on the capacitors connecting to the closed transferring switches are averaged and transferred to the TDI output through the feedback capacitor.

To accomplish the scanning process of one image point, five steps are needed before the averaging operation can be applied for this specific point. With the detailed timing diagram in Fig.5, the needed five steps are shown as follows.

Assuming the image point (donated as the red box in the diagram) is exposed to the first detector exactly in the first scanning step, sampling switches T11, T21 and T31 are closed, the output voltages from the three-pixel circuit are sampled on the corresponding capacitors. Specifically, the capacitor C11 captures the signal associated with the image point. The sampling switches are opened in the subsequent transfer phase, therefore the signal is frozen on the floating capacitor C11, which state is maintained for four steps until the averaging operation can be carried out.

In the second step, the sampling switches T12, T22, T31 are closed. But because the scanning step is limited to half the pixel pitch, none of the detectors can cover the image point.

In the third step, the image point is exposed to the second detector. At the same time, the sampling switches T13, T23, T31 are closed. Therefore, the signal associated with the image point can be sampled and frozen for two steps on the floating capacitor C23.

The operation in the fourth step is similar to that of the second step, except the sampling switches are changed to T14, T21, and T31.

In the fifth step, the image point is exposed to the third detector. With the closed switches of T15, T22, T31, the signal associated with the object can be sampled to the capacitor C31.

At this point, the signals sampled on the capacitor C11, C23 and C31 are available to enhance the SNR. The transferring switches TR11, TR23, and TR31 are closed, the stored signal is averaged and transferred to the TDI output.

For the next step, it is easy to infer that the signals sampled into the capacitor C12, C21, and C31 are just the right outputs resulting from the same exposed imaging point. Therefore, the averaging operation will be carried out continuously.

The output buffer is necessary to drive the highly resistive and capacitive load within the limited time for the multiplexed TDI output. As the TDI outputs are varied from different stages, the large-signal behavior, or slew rate characteristic is of importance for the output buffer.

To decrease the settling time, there are two feasible approaches. One can choose to increase the static bias current, or choose the push-pull output structure. The latter technique is adopted for the low power consideration. The simplified schematic is shown in Fig.6.

Part of the chip layout is shown in Fig.7. The chip was fabricated with a 0.35 μm CMOS process and occupies an area of 1.3 mm×20 mm. With the 5 V power supply, the power consumption is less than 60 mW.

To validate the CTIA pixel circuit, one external resistor is connected to the input, converting the applied voltage into the current. Fig.8 shows the voltage output directly from the CTIA circuit, it is clear to distinguish the reset phase and integration phases.

To validate the TDI stages, three different voltages are injected into the terminals Vi<1>, Vi<2>, and Vi<3>.Tab.1 summarizes the different combinations of three voltages and TDI output voltage. The averaging operation is realized successfully under all conditions.

In this paper, a 1024×3 TDI readout circuit is proposed and implemented. This readout circuit consists of capacitor trans-impedance amplifier (CTIA) pixel circuits, paralleled TDI stages, multiplexer, and output buffer. The chip was manufactured with a 0.35 μm CMOS process and occupies an area of 1.3 mm×20 mm. With the 5 V power supply, the power consumption is less than 60 mW. The measurement results validate the proposed design successfully.