In the digital chaotic secure communication network, the dynamic packet switching technology of digital chaotic signal plays an important role in improving the switching and transmission capacity of the optical chaotic network. In the optical chaotic packet switching node, the processing of optical chaotic signals involves multiplexing, demultiplexing, switching, regeneration, storage and so on. However, the premise of realizing the optical chaotic signal processing mentioned above is to have optical chaotic logic gates (such as logic NOT, AND, NAND, OR, NOR, XOR, XNOR) and digital chaotic bit computing devices (chaotic combinational logic operation devices and chaotic sequential logic operation devices) with low power, low loss and high speed. Therefore, in order to realize the digital chaotic signal dynamic packet switching technology, it is necessary to explore the low-loss and high-speed digital chaotic logic operation. Compared with traditional logic devices (such as digital circuit logic devices, optoelectronic logic devices, all-optical logic devices), chaotic logic operation devices have the characteristics of more security, more flexibility, lower power cost and so on. However, at present, most of the schemes implement the static chaotic logic operation, and the development of reconfigurable chaotic logic operation, chaotic combinational and sequential logic operation is still lagging behind. The external interference will not only affect the chaotic signal, but also may cause the system parameters to drift, change the output polarization state of the laser, resulting in the instability of the chaotic logic operation, and even errors. Therefore, it is of great value and significance to study the reconfigurable and storable chaotic logic operation with strong robustness and the ability of error detection and correction.In the implementation scheme of reconfigurable and storable chaotic logic operation, the normalized injection current of D-VCSEL is modulated as a logic input, and the applied electric field on PPLN₁ is modulated as a logic control signal. The logic outputs Z₁ and Z₂ are demodulated by a threshold mechanism for synchronization errors between the polarizations (x-PC_D1 and y-PC_D1) from the D-VCSEL and those (x-PC_R and y-PC_R) from R-VCSEL. The logic outputs Z₃ and Z₄ are obtained by demodulating the x-PC_D1 and the x-PC_R, respectively, based on threshold mechanism. The system can reconstruct and store the chaotic logic operations by transforming the logic operation relationship between the logic control signal and the logic input. It is found that when the noise intensity is 1×10⁹, the logic outputs Z₁ and Z₂ demodulated by the complete chaotic synchronization mechanism have more errors, but Z₃ and Z₄ have no errors. In order to improve the anti-noise performance of Z₁ and Z₂, the threshold mechanism is used to demodulate the synchronization error. When the noise intensity reaches 1.77×10⁹, the logic output will not generate bit errors. When the noise intensity reaches 1.84×10⁹, the logic outputs Z₁ and Z₂ generate bit errors, but the logic outputs Z₃ and Z₄ remain correct. If the noise intensity reaches 1.89×10⁹, the logic outputs Z₁, Z₂, Z₃ and Z₄ all have bit errors, and the logic operation fails. Therefore, the anti-noise performance of Z₃ and Z₄ is better than that of Z₁and Z₂. And if the noise intensity is in the range of 1.84×10⁹, the logic outputs Z₁ and Z₂ can be checked with Z₃ and Z₄ to realize error detection and correction processing.