A real-time design of a gigabit MAC based on a FPGA chip is proposed to resolve the high-speed image data transmission problems existing in the airborne integration design of a high-frame-rate camera. A gigabit network card composed of an ethernet media access control(MAC) and an external PHY is designed to realize the real-time high-speed transmission of video and image data of the high-frame-rate camera. A synchronous FIFO in the gigabit MAC core is designed using a FPGA-chip-embedded block RAM. The FIFO is designed using the Verilog HDL, synthesized in the ISE design environment of XILINX FPGA and simulated in Modelsim. The results show that the FIFO can be written and read with correct produced flag signals at a writing and reading clock of 250MHz and that the FIFO can realize the function of data cache. The feasibility of the proposal is verified in both simulation and real test.