A third-order hybrid structure noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter(ADC) was designed. The hybrid structure consisted of two stage, a cascaded integrator feed-forward (CIFF) stage and a second-order error feedback (EF) stage. This structure was used to control the feedback residue and enhance the order of the noise transfer function, achieving a three-order noise transfer function. And the Vcm-based switching mode was used to optimize the dynamic offset voltage of comparator. The circuit was designed in a 0.35 μm CMOS process. It consumes 1.87 mW power when operating at a 2 MS/s sampling frequency and an oversampling ratio of 8 with a 3.3 V supply. The proposed NS SAR ADC achieves a 87.93 dB SNDR and a 14.3 bit ENOB, enhancing the ENOB by 6.3 bit on the basis of traditional 8-bit SAR ADC.

A high-resolution and low-power noise-shaping SAR ADC with segmented dynamic element matching (DEM) was designed. It realized a second-order noise-shaping filter with passive gain to enhance the noise-shaping capability. Besides, a segmented DEM circuit was proposed to solve the problem of harmonic distortion caused by the DAC capacitor mismatch to further improve the signal-to-noise-and-distortion ratio (SNDR) of the ADC. The simulation results show that the designed noise-shaping SAR ADC achieves 91.1 dB SNDR at the sampling rate of 4 MS/s and the oversampling ratio (OSR) of 40. The designed ADC consumes 231 μW at 1.8 V supply voltage, achieving Schreier figure of merit (FOM) of 174.5 dB.

In the pipeline ADC circuit, the nonlinear capacitance in the gate-voltage bootstrap switch has a direct effect on the on-resistance of the switch, resulting in nonlinear sampling. In this paper, a three-path gate voltage bootstrap switch with high linearity was designed. Three bootstrap capacitors were used to form two main paths and one auxiliary path, which speeded up the gate voltage establishment when the input signal was transmitted to the gate end of the switch through the two main paths. Thus, the signal driving ability was enhanced and the accuracy of the overall circuit was improved. The designed gate-voltage bootstrap switch was used in the sample-and-hold circuit of a 14 bit 500 MHz pipelined ADC. The circuit was designed in TSMC 28 nm CMOS process. The simulation results show that the signal-to-noise ratio (SNDR) of the proposed gate voltage bootstrap switch is 92.85 dB and the spurious free dynamic range (SFDR) is 110.98 dB when the input frequency is 249 MHz and the sampling frequency is 500 MHz.

In order to meet the requirement of high speed and high precision sampling under low voltage conditions, a voltage-time domain two-stage hybrid structure pipeline analog-to-digital converter (ADC) was designed. The first stage of the pipeline ADC, which was a successive approximation type (SAR) ADC, converted the voltages into 8 bit digital signals. After the residual voltage was transformed into time-domain delay information, the second stage 4.5 bit time-to-digital converter (TDC) converted the delay information, and the final calibrated output achieved 12 bit precision conversion. By using multiple voltage supplies, improving residual voltage transfer and amplifier structure, and optimizing the time decider, the dynamic performance and sampling speed of the ADC has been improved, and the sampling power consumption has been reduced. The ADC was designed and simulated in a 40 nm CMOS process. The power consumption is 9.5 mW at a sampling rate of 200 MS/s, the dynamic indexes SNDR, SFDR is 68.4 dB, 83.6 dB respectively, and the figure of merit 22 pJ·conv-1·step-1 , which can meet the application requirements of low power and high speed sampling.

The poor nonlinearity of the tapped delay chain cascaded by Carry4 units in FPGA is one of the important problems to be solved in TDC measurement system. Based on the existing tapped sampling sequence (" SCSC "), a method of "mixed" tapped sampling sequence was proposed to solve this problem, and the non-uniformity of delay units was significantly improved. The built TDC consisted of modules such as tapped delay chain, sampling and coding logic circuit, and code density calibration, and was verified on a Xilinx Kintex-7 series chip. The experimental results show that the differential nonlinearity of this method is reduced by 32.0% and the integral nonlinearity is reduced by 22.8% compared with that of the "SCSC" sequence. Through further calibration, the achieved resolution (LSB) of TDC is 13.51 ps, the measurement accuracy is 19.17 ps, the differential nonlinearity range is ［-0.45,0.96］LSB, and the integral nonlinearity range is ［-3.27,1.33］LSB.

A bandgap reference with high-order temperature compensation and built-in negative feedback voltage regulation was designed. Low temperature drift and high PSRR were achieved in the proposed bandgap reference. By using two pairs of MOS transistors working in the subthreshold region, the exponential compensation current was generated according to different operating temperature, which resulted in a high-order temperature compensation and hence reduced the temperature coefficient of the bandgap reference. Based on the output voltage of the bandgap reference, the power supply rejection capability of the bandgap reference was improved by building a negative feedback voltage regulator. Based on the Dongbu 0.18 μm BCD process, a low-temperature-coefficient and high-PSRR bandgap reference was completed. The layout area of the proposed bandgap reference was 290 μm×200 μm. The post simulation results show that the temperature coefficient is only 1.15×10-6/℃ in the temperature range of -45 ℃ to 125 ℃, and the PSRR reaches 83.22 dB. The average output voltage is 1.212 V and the line sensitivity is 0.015% in the supply range of 2.8-5.5 V.

A 40 V high-voltage output auto-zero operational amplifier was designed and implemented in a 0.6 μm BCD process. A time-interlaced auto-zero structure was utilized to achieve continuous calibration of the input offset voltage. A high-voltage class AB stage based on 40 V PDMOS and NDMOS transistors was utilized at the output stage. The input stage and auto-zero calibration circuit of the operational amplifier were based on 0.6 μm standard MOS transistor which operated on a single 5 V power supply. The middle amplification stage and output stage utilized 40 V DMOS with asymmetric structure to realize high-voltage output. In the overall circuit, only the drain-source voltage of DMOS transistors withstood a voltage of 40 V, and the voltage under the other MOS transistors was within the proper power supply range, so there was no voltage to withstand exceeding risk. The pre-simulation results show that the operational amplifier operates under 5 V and 40 V dual power supply, and the input offset voltage is 0.78 μV. The output voltage range is 3.0-37.7 V. The equivalent DC gain is 142.7 dB. The unit gain bandwidth is 1.9 MHz. The common mode rejection ratio is 154.8 dB. The 40 V power supply rejection ratio is 152.3 dB, and the 5 V power supply rejection ratio is 134.9 dB.

In the SerDes circuits, the key of high speed data transmission is the equalized rate, so as the rate of data transmission increased, the rate of the decision feedback equalizer in the receiver of SerDes are also increasing. As a key component of adaptive decision feedback equalizer, delay time of the comparator determines the rate tolerance of the adaptive decision feedback equalizer. In order to meet requirement of low voltage for high speed comparator, this paper proposed a new comparator circuit which is suitable for high speed decision feedback equalizer. Based on a traditional two-tail comparator, this new comparator circuit was designed in TSMC 28 nm CMOS process. When the supply voltage is 1 V, the average delay time is 52.58 ps. It can meet the requirements of the decision feedback equalizer which data rate is up to 15 Gbit/s.

A high precision and low noise operational amplifier was designed and implemented. A base current elimination technique was proposed to compensate the base current of the input transistor pairs, which reduced the input bias current of the operational amplifier effectively. So the input noise voltage was reduced by increasing the collector current of the input transistors, achieving a lower total equivalent input noise of the operational amplifier. At the same time, the collector-emitter voltage compensation circuit was used to eliminate the influence of the Early effect and improve the circuit accuracy. The chip was designed and fabricated in a 36 V complementary bipolar process. The measurement results show that the offset voltage of the chip is 6.94 μV, the voltage noise density at 1 kHz is 5.6 nV/Hz, and the current noise density is 0.9 pA/Hz.

A single-stage MMIC PA with a center frequency of 75 GHz was designed, which was fabricated based on the InP DHBT in a 0.8 μm process. The ft/fmax of the device was 171/250 GHz. This circuit used a two-layer common-base stack structure, in which the lower CB layer was directly grounded at the base. The emitter at the input port was supplied with a negative voltage of -0.96 V, and the bias voltage Vc2 was 4 V. In order to increase the output power, the devices in the upper and lower layers were in parallel with four fingers. Furthermore, the same devices were used to design a stack structure with a common emitter below. The CB stack was compared with international stack structure circuits manufactured in advanced InP processes , while the CB stack structure had better performances than the CE stack in terms of gain and peak PAE.

An approximate multiplier based on static segment method was proposed. The partial product array was generated by modified Booth encoding method based on static segment method. After Booth encoding, the generated partial product array was optimized with error compensation and compressed by approximate compressing tree to achieve a compromise between hardware performance and accuracy. The simulation results show that, compared with the full-precision multiplier generated by the EDA tool, the proposed design reduces the area and power consumption by 36.96% and 35.95% respectively while maintaining high precision. In the application of image edge detection, the peak signal-to-noise ratio and structural similarity index of the proposed design are 26.10 and 98% respectively, indicating that the application result is close to that of full-precision multiplier while reducing hardware resource consumption.

With the rapid development of the cloud computing, internet of things and artificial intelligence, terminal devices are facing great challenges in hardware resources and power consumption. In order to reduce the power consumption of computing units, two kinds of low power approximate 8-bit multipliers based on novel 4-1 compressors were proposed. Based on analysis of the errors of 4-1 compressors, an error compensation module was designed to reduce the precision loss. The simulation results show that, compared with the exact multiplier, the delay of the proposed multipliers was reduced by 5.67% and 18.23%, the area by 6.54% and 20.36%, and the power consumption by 15.83% and 30.94%, respectively. Finally, the proposed multipliers are applied to image sharpening, which verify its validity in error-tolerant applications.

A novel power-rail electrostatic discharge (ESD) clamp circuit was proposed, which aimed to solve the issue of the insufficient turn-on duration of RC trigger-mechanism under the small capacitance condition. This circuit used a method of feedback and shunt mechanisms combined with a capacitance, in which a small capacitance was in parallel to a shunt nMOS controlled by another feedback nMOS. The shunt nMOS diverted the capacitance charging current, so the turn-on duration of the circuit was prolonged. The simulation results show that the turn-on duration of the proposed circuit is enough long, and can respond quickly to the ESD event, which can achieve ESD protection. Furthermore, the proposed circuit with an adjustable minimum starting voltage (Vstarting) could effectively avoid the false trigger under the fast power-on condition.

With the continuous development of IC industry and the continuous pursuit of high energy efficiency, the process size is constantly shrinking. More and more circuits work in the sub-threshold domain, and the fluctuation of process parameters leads to the non-Gaussian distribution of circuit delay. Statistical static timing analysis is a new method to analyze the timing in advanced process, which can accelerate timing convergence and display the expected yield by adopting a method of expressing process parameters and delay with random variables. This paper mainly studied the statistic modeling method of circuit cell delay fluctuation in sub-threshold domain. The models of Monte Carlo gold standard data for single timing arc and multiple timing arcs were built up respectively. A distributed fitting statistical modeling method for single timing arc cell delay is proposed, and the error is less than 6.30%. An artificial neural network statistical modeling method for multiple timing arcs cell delay is proposed, and the error is less than 4.95%.

Convolutional neural network ZynqNet is widely used in edge devices. However, the existing FPGA hardware acceleration schemes are not able to meet the real-time requirements of high-demand scenarios, as their frame rates are limited to less than 30 FPS. This paper focuses on the improvement of ZynqNet's FPGA acceleration performance by designing a parallel computing structure based on multiple feature blocks, optimizing support for Expand layer to enhance feature reuse, and optimizing output cache to reduce the number of memory accesses efficiently. Furthermore, A depth-first feature and weight cache mechanism is proposed, utilizing a multi-bank cache mode to enable one-cycle feature and weight reading. Based on the Xilinx Xc7z045 FPGA chip, the accelerator hardware implementation and performance test are completed, the operating frequency is 166 MHz, and the computing performance can reach 49 FPS. Compared to the traditional scheme of deploying the entire network to FPGA, the proposed approach delivers three times the acceleration and five times the improvement in energy efficiency ratio.

In UAV 3D terrain mapping, the time-to-digital converter (TDC), which is the core module, needs to have long-range measurement capability and high measurement resolution. Based on the comprehensive consideration of the long range, kilometer-level ranging capability and centimeter-level measurement accuracy of the ranging system, a low power multi-phase clock generation circuit for TDC was designed in this paper. A pseudo-differential ring voltage controlled oscillator was used in this design. By optimizing the cross-coupling structure, the slope of the signal edges was improved, and the jitter performance of the clock and the suppression of power supply noise were enhanced while ensuring low power consumption. In the charge pump design, a very low bias current was selected by considering the loop bandwidth to further reduce power consumption while reducing the area of the loop filter. The multi-phase clock generation circuit was designed in SMIC 180 nm CMOS process. The simulation results show that the loop bandwidth is stable at 1 MHz at an output frequency of 400 MHz. The circuit achieves a fast locking speed at different process corners, with a phase noise of -88 dBc@1 MHz, a power consumption of 1 mW, and a root mean square jitter of 27 ps, meeting the accuracy requirements of centimeter-level ranging.

Due to the different internal driving voltages required by the computing-in-memory array of flash memory in the working mode, an adjustable charge pump for the array was designed based on various Dickson charge pump. A new cross-coupled design was adopted for the output stage to reduce the low pumping efficiency caused by the threshold voltage of the last stage in traditional charge pump. At the same time, the auxiliary MOS transistor was used to enhance the ability of the body-source diode in the traditional charge pump to suppress reverse leakage. The simulation results in a 55 nm CMOS process show that compared with the traditional charge pump, the reverse leakage of the intermediate stage is reduced by 17.5%, and the reverse leakage of the output stage is reduced by 73.1 % under a power supply voltage of 1.8 V and a working current of 300 μA. The maximum output voltage of the main charge pump is 9.56 V, and the voltage efficiency is 88.51% without feedback regulation. In the PFM adjustable mode, the reconfigurable charge pump can realize output voltage switching.

A single-inductor three-output boost DC-DC converter was designed. The converter adopted the average current mode with the output voltages of all branches being linearly added to form the common-mode feedback signal for loop compensation. A switch capacitor sampling network was proposed. The output voltage was sampled, and the sampled voltage was compared with the reference voltage to correct the DC offset between the output voltage and the reference voltage. To suppress the cross-regulation among output branches, a novel energy control logic circuit was proposed, which could realize the cyclic charging of each output branch within a single inductor charge-discharge cycle. The boost converter was designed in a 0.18 μm CMOS process. The simulation results show that the first two output branches suffer from no cross-regulation and the impact on the third output branch can be effectively alleviated with a 100 mA load transient change.

An on-chip low dropout linear regulator (LDO) with high gain and stability was proposed. It could provide fast-response voltage for high speed changing logic and driver circuits. The two-stage cascaded output LDO with a wide supply voltage range from 9.5 V to 15.5 V was designed in a 0.18 μm BCD process, which had a good phase margin, a high response speed and a good linear adjustment rate to meet the power supply requirements of multiple power rails inside the chip. The LDO circuit was simulated with Cadence, and was fabricated. The simulation and test results show that the main loop of LDO has a good phase margin and a low output voltage ripple in the full load range. When the input voltage ranges from 9.5 V to 15.5 V, the output voltages of the two-stage LDO are stable at 4.53 V and 1.80 V, respectively, and the linear regulation is nice. The LDO can provide stable supply voltages for logic, driver and other modules when used in GaN driver chips.

A fast transient response output capacitor-less LDO circuit with slew rate enhancement was designed. The error amplifier adopted a current mirror transconductance structure, which reduced the difficulty coefficient of frequency compensation. In addition, a transient enhanced circuit that can provide additional charge and discharge current for the power transistor was designed, which demonstrated a quick response to the change of load, increased the slew rate, and effectively improved the load transient response. The simulation results show that the proposed circuit can achieve a phase margin larger than 60° among the full load range with only Miller compensation. Moreover, if the load jumps between 100 μA and 100 mA within 0.5 μs, the undershoot and overshoot voltage are 69 mV and 64mV respectively, and the settling time is 0.89 μs and 0.86 μs respectively. The undershoot and overshoot voltage are attenuated by 73% and 78% respectively compared with the one without a transient enhanced circuit, and the load transient response is significantly improved.

A motor driver with low power consumption and wide supply voltage range was designed. By adopting the high efficiency pump circuit and designing new charge pump power supply mode, the motor driver circuit could be implemented to achieve a wide supply voltage range and low power consumption. The driver ensured that the power tube still had a low on resistance and a large output drive current at low voltage, and the power tube gate source will not break down at high voltage. The charge pump clock control circuit was designed, so that the driver had a lower power consumption. This circuit was designed in SMIC 180 nm BCD process. The simulation results show that the motor driver has a motor power input range of 0 V to 15 V, a logic supply range of 1.8 V to 5.5 V, and a quiescent power consumption of 284.5 μA.

The power management chip is responsible for the transformation, distribution, detection and other power management of electrical energy in the electronic equipment system. The most common structures of which are linear power supplies and switching power supplies. The switching power supply can maintain a stable output voltage by controlling the MOSFET switch opening and closing time. It is widely used in almost all electronic equipment because of its high efficiency and miniaturization characteristics. There are often multiple voltage rails in industrial control systems, automotive electronics and other fields. In different working stages, there is also a large range of input voltage instantaneous transformation, which makes it require high input voltage at the same time. It is necessary to power the loads efficiently over a wide input range. In this paper, the conversion efficiency improvement of wide input voltage DC-DC, fast response technology and low EMI design are comprehensively described, and some recent advances in academia and industry are analyzed.

A millimeter-wave AlN/GaN MIS-HEMT device for low operating voltage application is proposed. An epitaxial material was redesigned, and an AlN barrier epitaxial layer was grown on the SiC substrate. Based on this SiC substrate, several MIS-HEMT devices were fabricated. The ohmic contact process was optimized in the aspect of high temperature RTA. The DC tests were performed for the fabricated devices. The results show that the maximum drain current is 2.4 A/mm, the extrinsic peak gm is 518 mS/mm, the small signal ft is 85 GHz, and the fmax is over 141 GHz. The large signal tests at 28 GHz of 5G millimeter-wave band show that the output power density (POUT) is 0.55 W/mm, and the power additional efficiency (PAE) is 40.1% at VDS = 3 V. At VDS = 6 V, the POUT is 1.6 W/mm, and the PAE is 47.8%. The AlN/GaN MIS-HEMT device demonstrate its potential in future millimeter-wave applications.

Junctionless nanotube field effect transistors (JLNT-FET) and inversion-mode nanotube field effect transistors (IMNT-FET) cause widespread attention for their better driving capability and excellent suppression of short channel effect (SCE), and self-heating effect (SHE) is widely studied as a key issue affecting their electrical and thermal performance. In this paper, the effects of conduction mechanisms on the electro-thermal characteristics in JLNT-FET and IMNT-FET were comparatively investigated by analyzing the effects of ambient temperature (TA), thermal contact resistance (Rtc), and spacer length (LS) on device parameters such as maximum lattice temperature (TLmax), maximum carrier temperature (TCmax), drain current (IDS), and gate leakage current (IG) of the bulk-conducting JLNT-FET and surface-conducting IMNT-FET based on TCAD numerical simulator. The results show that higher TA, larger Rtc, and smaller LS exacerbate phonon scattering which leads to severe SHE. Meanwhile, due to the difference of conduction mechanisms, the body conduction is less affected by interface scattering and phonon scattering, and JLNT-FET has better electrothermal characteristics.

A structure with floating electrodes in the trench sidewall oxide layer of shielded gate trench MOSFET (SGT structure) is proposed to optimize the specific on-resistance and the specific gate-drain capacitance by improving the electric field distribution. Based on the conventional SGT structure, the floating electrode structure with a breakdown voltage of 141.1 V, a specific on-resistance of 55 mΩ·mm2 and a specific gate-drain capacitance of 4.72 pF·mm-2 is finally obtained by increasing the doping concentration of the epitaxial layer, and changing the length and position of the floating electrodes and the thickness of the oxide layer. Compared with the SGT structure with the same structural parameters, the specific on-resistance of the floating electrode structure is decreased by 9.3%, the Baliga’s figure of merit is increased by 13%, and the specific gate-drain capacitance is decreased by 28.4% under the same breakdown voltage.

In order to study the nonlinear motion of the cantilever beam of capacitive MEMS microwave power sensor, the bending characteristic model of the MEMS cantilever beam in space domain was established. Considering the effects of electrostatic force, axial stress and residual stress on the nonlinear motion of the cantilever beam, a dynamic differential equation was obtained. On this basis, the bending characteristics of the cantilever beam under different Young's modulus, driving voltage and residual stress were studied. And the corresponding bending characteristic curve and axial stress curve of cantilever beam were obtained. Meanwhile, the finite element analysis software ANSYS was used to simulate the pull-down displacement of cantilever beam with different driving voltages, and the simulation results were compared with the analytical results. The results show that when the driving voltage changes from 10 V to 20 V, the simulation results are consistent with the model analysis results, and the maximum error is only 8.81%. Therefore, this work has a certain reference value and guiding significance for the research of cantilever bending characteristics of capacitive MEMS microwave power sensor.

Aiming at the chip crack problem of K1-5 shell using No. 10 steel as the substrate, the eutectic stress was simulated, and the procedure was optimized. The results show that no matter how slow or fast heat dissipation is adopted, the thermal stress caused by the huge difference in thermal expansion coefficient between No. 10 steel and Si chip can not be fundamentally changed. By comparing three different shell materials, it can be seen that the thermal stress of the K1-5 shell with Kovar material as the matrix is the lowest, 316 MPa, while the No. 10 steel is the highest, 19 800 MPa, far beyond the limit breaking strength of silicon chip 544 MPa. According to the basic theory of stress, and comparing the difference between the thermal expansion coefficient of the three materials and Si chip, it is found that the difference in the thermal expansion coefficient of Kovar and Si chip is the smallest, followed by oxygen-free copper, and No. 10 steel is the largest, which is the fundamental reason for chip cracking when sintering K1-5 shell with No. 10 steel as the matrix. From simulation analysis and practical experiments, it has been proved that replacing the shell with Kovar material can effectively solve the problem of chip cracking.

Silica gel has cracking phenomena on the side wall of nickel-plated tube shell, which mainly includes glue dot cracking during the first adhesion processing, cracking after a single cleaning, cracking after random vibration in reliability experiment, etc. Those cracking issues will further lead to a series of reliability problems such as connection failure. In this paper, the theoretical calculation of the ultimate destructive force of bonding, the simulation calculation of adhesive with different dot diameters and different spacing adhesives, and the surface energy improvement caused by plasma cleaning were carried out in view of the cracking problem of Ni-plated shell sidewall reinforcement of type A silica gel. The results show that optimizing the bonding structure of the wire-glue module and cleaning of the nickel-plated shell with plasma can significantly improve the reliability of the sidewall bonding of type A silica gel on the sidewall of the nickel-plated shell. The relevant research results can be used in the actual production practice of A type silica gel.