[1] I Park, W Jo, C Park et al. A 640 × 640 fully dynamic CMOS image sensor for always-on operation. IEEE J Solid State Circuits, 55, 898(2020).

[2] T H Hsu, Y R Chen, R S Liu et al. A 0.5-V real-time computational CMOS image sensor with programmable kernel for feature extraction. IEEE J Solid State Circuits, 56, 1588(2021).

[3] S Hanson, Z Foo, D Blaauw et al. A 0.5 V sub-microwatt CMOS image sensor with pulse-width modulation read-out. IEEE J Solid State Circuits, 45, 759(2010).

[4] N Couniot, G de Streel, F Botman et al. A 65 nm 0.5 V DPS CMOS image sensor with 17 pJ/Frame. Pixel and 42 dB dynamic range for ultra-low-power SoCs. IEEE J Solid State Circuits, 50, 2419(2015).

[5] K B Cho, A I Krymski, E R Fossum. A 1.5-V 550-μW 176 × 144 autonomous CMOS active pixel image sensor. IEEE Trans Electron Devices, 50, 96(2003).

[6] J Choi, J Shin, D W Kang et al. Always-on CMOS image sensor for mobile and wearable devices. IEEE J Solid State Circuits, 51, 130(2016).

[7] Y Nitta, Y Muramatsu, K Amano et al. High-speed digital double sampling with analog CDS on column parallel ADC architecture for low-noise active pixel sensor. 2006 IEEE International Solid State Circuits Conference, 2024(2006).

[8] Q Y Liu, A Edward, M Kinyua et al. A low-power digitizer for back-illuminated 3-D-stacked CMOS image sensor readout with passing window and double auto-zeroing techniques. IEEE J Solid State Circuits, 52, 1591(2017).

[9] I Park, C Park, J Cheon et al. A 76mW 500fps VGA CMOS image sensor with time-stretched single-slope ADCs achieving 1.95e- random noise. 2019 IEEE International Solid-State Circuits Conference, 100(2019).

[10] H J Kim. 11-bit column-parallel single-slope ADC with first-step half-reference ramping scheme for high-speed CMOS image sensors. IEEE J Solid State Circuits, 56, 2132(2021).

[11] B Shin, S Park, H Shin. The effect of photodiode shape on charge transfer in CMOS image sensors. Solid State Electron, 54, 1416(2010).

[12] Y Xu, A J Theuwissen. Image lag analysis and photodiode shape optimization of 4T CMOS pixels(2013).

[13] X Z Cao, D Gäbler, C Lee et al. Design and optimization of large 4T pixel(2015).

[14] F Acerbi, M M Garcia, G Köklü et al. Transfer-gate region optimization and pinned-photodiode shaping for high-speed ToF applications(2017).

[15] T C Millar, N Sarhangnejad, N Katic et al. The effect of pinned photodiode shape on time-of-flight demodulation contrast. IEEE Trans Electron Devices, 64, 2244(2017).

[16] S Kawahito. Column-parallel ADCs for CMOS image sensors and their FoM-based evaluations. IEICE Trans Electron, E101.C444(2018).

[17] K M Nie, W B Zha, X L Shi et al. A single slope ADC with row-wise noise reduction technique for CMOS image sensor. IEEE Trans Circuits Syst I, 67, 2873(2020).

[18] H Park, C Z Yu, H Kim et al. Low power CMOS image sensors using two step single slope ADC with bandwidth-limited comparators & voltage range extended ramp generator for battery-limited application. IEEE Sens J, 20, 2831(2020).